1. Field of the Invention
The present invention relates to a method of processing interrupt requests, for receiving interrupt requests from a plurality of peripheral input/output devices and for processing interrupt requests sequentially according to their interrupt priorities, and an information processing apparatus using-the method.
2. Description of the Prior Art
Referring now to FIG. 7, there is illustrated a block diagram showing the structure of a prior art information processing device using a prior art method of processing interrupt requests. In the figure, reference numeral 701 denotes an interrupt control unit (ICU) which receive interrupt signals 104 from a plurality of peripheral input/output devices (not shown in the figure) so as to select the interrupt signal 104 with the highest priority from them and then furnish an interrupt request signal (IRQ) 106 which corresponds to the selected interrupt signal 104, 702 denotes a central processing unit (CPU) which, in response to the IRQ 106 from the ICU 701, completes a series of processes which have been being executed, and, after that, executes a process called an interrupt preprocessing which corresponds to the interrupt request and a microprogram to handle the interrupt request, i.e., an interrupt handler, 103 denotes a memory device for storing the interrupt handler, the address indicating the origin of the interrupt handler (i.e., interrupt vector), and so on, 105 denotes an interrupt mask level signal (IMASK) which is furnished to the ICU 701 by the CPU 702, 707 denotes a read signal (READ) which is furnished to the ICU 701 by the CPU 702 in order for the CPU to read the contents in an interrupt information register (not shown) disposed within the ICU, 110 denotes an address bus, 111 denotes a data bus, 114 denotes a signal line for electrically connecting the ICU 701 to the address bus 110, 115 denotes a signal line for electrically connecting the CPU 702 to the address bus 110, 116 denotes a signal line for electrically connecting the memory device 103 to the address bus 110, 117 denotes a signal line for electrically connecting the ICU 701 to the data bus 111, 118 denotes a signal line for electrically connecting the CPU 702 to the data bus 111, and 119 denotes a signal line for electrically connecting the memory device 103 to the data bus 111.
Referring next to FIG. 8, there is illustrated a timing chart showing the operation of the prior art information processing apparatus of FIG. 7 using the conventional interrupt request processing method. A description will be made as the operation of the prior art information processing apparatus with reference to FIGS. 7 and 8.
Each of the plurality of peripheral input/output devices (not shown) can furnish an interrupt signal 104 to the information processing apparatus. The interrupt signal 104 is a signal which is asserted HIGH or LOW to request an interruption. The ICU 701 having a function of clearing the interrupt signal 104 from one peripheral input/output device which is an interrupt request source selects the interrupt signal 104 with the highest priority from the plurality of interrupt signals 104 received. Furthermore, the ICU 701 compares the interrupt priority assigned to the selected interrupt signal 104 with the interrupt mask level indicated by the IMASK 105 delivered by the CPU 702. As a result, if the interrupt priority of the interrupt signal 104 is greater than the interrupt mask level, the ICU 701 furnishes the IRQ 106 which corresponds to the selected interrupt signal 104 to the CPU 702. Then, the ICU 701 writes an interrupt priority level 901 assigned to the IRQ 106 which is delivered to the CPU 702 and an interrupt vector table address (VCTABADR) 902 showing the address of an interrupt vector table storing the address specifying the origin of the corresponding interrupt handler into its interrupt information register (not shown in FIG. 7), as shown in FIG. 9.
When the CPU 702 receives the IRQ 106 from the ICU 701, it completes a series of processes 816 shown in FIG. 8 which have been being executed just before it receives the IRQ 106 and, after that, starts a process called an interrupt preprocessing in order to process the interrupt request. First, the CPU 702 saves or clears the value of the program status word in clock cycle 801. Then the CPU 702 furnishes the READ 707 to enable the ICU 701 to send out the interrupt priority level 901 and VCTABADR 902 as shown in FIG. 9 on the data bus 111, so that the CPU 702, in clock cycles 802 and 803, reads the interrupt priority level 901 and VCTABADR 902 on the data bus 111.
After that, the ICU 701 causes the IRQ 106 to make a HIGH to LOW transition, so that the IRQ 106 is deactivated. On the other hand, the CPU 702 copies the interrupt priority level 901 to the program status word in clock cycle 804, and then expands the 16-bit VCTABADR 902 to a 32-bit interrupt vector table address in clock cycle 805. Next, the CPU 702, in clock cycle 806, sends out the expanded VCTABADR 902 showing the memory location at which the address specifying the origin of the interrupt handler which can handle the interrupt request is stored on the address bus 110 by way of the signal line 115, and then reads, by way of the signal line 118, the address specifying the origin of the interrupt handler which is delivered on the data bus 111 by the memory device 103. After that, the CPU 702 continues to perform the interrupt preprocessing and then executes the interrupt handler following the completion of the interrupt preprocessing.
In the operation, the IRQ 106 from the ICU 701 makes a transition to its deactivated state when the CPU 702 finishes reading the contents in the interruption information register of the ICU 701. Simultaneously, the interrupt priority level 901 is cleared. Furthermore, in the mode wherein it is determined that while the interrupt signal 104 applied is asserted HIGH or LOW, the interruption is enabled, whereas while the interrupt signal 104 is at the reversed state, the interruption is disabled, when the corresponding peripheral input/output device clears the interrupt signal 104, the ICU 701 causes the IRQ 106 to make a transition to its deactivated state.
When the interrupt request source cancels the interrupt request so as to clear the interrupt signal 104 and then cause the IRQ 106 to make a transition to its deactivated state before the CPU 702 finishes reading the contents in the interrupt information register in response to the IRQ 106, the CPU cannot initiate the proper interrupt handler. To avoid this malfunction, a measure to start a given interrupt handler when the CPU comes upon the situation is taken.
Referring next to FIG. 10, there is illustrated a block diagram showing the structure of an information processing apparatus using another conventional interrupt processing method as disclosed in Japanese Patent Application Laying Open (KOKAI) No. 2-263256. In the figure, the same components as the information processing apparatus shown in FIG. 7 are designated by the same reference numerals, and therefore the description about the components will be omitted hereinafter. In FIG. 10, reference numeral 107 denotes an interrupt request acknowledge signal (IRQACK). The CPU 702 furnishes the IRQACK 107 to the ICU 701 in response to the IRQ 106 from the ICU 701.
The ICU 701 selects one interrupt signal 104 with the highest interrupt priority from a plurality of interrupt signals 104 received according to their interrupt priorities. Then the ICU 701 furnishes the IRQ 106 which corresponds to the selected interrupt signal 104 with the highest interrupt priority to the CPU 702 so as to initiate an interrupt receiving process. When the CPU 702 receives the IRQ 106 from the ICU 701, the CPU 702 completes a series of processes which have been being executed Just before the CPU 702 receives the IRQ 106, and, after that, causes the IRQACK 107 to make a LOW to HIGH transition to acknowledge receipt of the interrupt. When the ICU 701 then detects that the IRQACK 107 makes a LOW to HIGH transition, it sends out an interrupt vector, i.e., an address specifying the origin of the interrupt handler on the address bus 110 by way of the signal line 114.
When the memory device 103 reads the interrupt vector on the address bus 110 by way of the signal line 116, the memory device 103 sends out an instruction addressed by the interrupt vector, i.e., the first instruction code of the interrupt handler on the data bus 111 by way of the signal line 119. The CPU 702 reads the instruction code via the data bus and then starts to execute the interrupt handler.
In Japanese Patent Application Laying Open (KOKAI) No. 2-263256, there is no description about how the CPU 702 processes the interrupt request when the corresponding interrupt source clears the interrupt signal 104 and then causes the IRQ 106 to make a transition to its deactivated state so as to cancel the interrupt request before the CPU 702 finishes reading the interrupt vector in response to the IRQ 106.
Since such a prior art information processing apparatus using a conventional interrupt processing method is so constructed as mentioned above, there is a problem in that a proper interrupt handler cannot be executed if the peripheral input/output device which is a corresponding interrupt request source clears the interrupt signal before the CPU 702 which has detected the generation of the IRQ 106 finishes reading the contents in the interrupt information register, or before the CPU 702 finishes reading the interrupt vector.